Embodiments of the present invention relate to a method for manufacturing an array substrate of liquid crystal display, and more particularly to a method for manufacturing an array substrate of liquid crystal display capable of reducing the over-etching.
Nowadays, an array substrate of liquid crystal display panel is typically manufactured by photolithographic process and since the mask employed by the photolithographic process is expensive, reducing the number of the masks to be used is a key for reducing the cost and enhancing the competitive ability.
Several methods have been proposed for reducing the number of the masks employed in the photolithographic process. For example, there is proposed a method in which the transparent electrode (formed by ITO, IZO and the like), the source electrode, the drain electrode and the thin film transistor (TFT) channel are formed through a dual tone mask. The method can be applied to manufacture array substrates for the twist nematic (TN) type liquid crystal display, the fringe field switching type liquid crystal display and the like.
The conventional method for manufacturing an array substrate of TN type liquid crystal display by four photolithographic processes specifically comprises the following steps:
Step 1 of depositing a gate metal layer on a substrate, forming a gate line through a first mask by a first photolithographic process, and forming a gate electrode which could be extended from and integrated with the gate line depending on the requirements;
Step 2 of depositing a gate insulating layer, an active layer (a semiconductor layer and a doped semiconductor layer) on the substrate after step 1 and forming an active layer pattern through a second mask by a second photolithographic process;
Step 3 of depositing a transparent conductive layer and a source/drain metal layer in this order on the substrate after step 2 and forming a pixel electrode, a source electrode, a drain electrode and a TFT channel through a third mask (a dual-tone mask) by a third photolithographic process;
Step 4 of depositing a passivation layer on the substrate after step 3 and forming a passivation layer pattern and via holes through a fourth mask by a fourth photolithographic process.
In addition, the conventional method for manufacturing an array substrate of FFS type liquid crystal display by four photolithographic processes specifically comprises the following steps:
Step 1 of depositing a gate metal layer on a substrate, forming a gate line through a first mask by a first photolithographic process, and forming a gate electrode which could be extended from and integrated with the gate line depending on the requirements;
Step 2 of depositing a gate insulating layer, an active layer (a semiconductor layer and a doped semiconductor layer) on the substrate after step 1 and forming an active layer pattern through a second mask by a second photolithographic process;
Step 3 of depositing a first transparent conductive layer and a source/drain metal layer in this order on the substrate after step 2 and forming a pixel electrode, a source electrode, a drain electrode and a TFT channel through a third mask (a dual-tone mask) by a third photolithographic process;
Step 4 of depositing a passivation layer and a second transparent conductive layer on the substrate after step 3 and forming a passivation layer pattern, via holes and a common electrode through a fourth mask by a fourth photolithographic process.
In the above-described methods for manufacturing the array substrate of liquid crystal display, the pixel electrode, the source electrode, the drain electrode and the TFT channel are formed through one dual-tone mask by one photolithographic process so that the production cost is reduced. However, it is found that the display quality of liquid crystal display may suffer by using the above methods, which will be described in detail as follows.
Referring to FIG. 1 and FIG. 2A to FIG. 2G, in which FIG. 1 is a structural schematic view showing a conventional array substrate of liquid crystal display; FIG. 2A is cross section view showing a conventional substrate formed with a gate electrode, a gate insulating layer and an active layer pattern after depositing a first transparent conductive and a source/drain metal layer; FIG. 2B is a cross section view showing the substrate after exposing and developing the photoresist on the substrate of FIG. 1 through a dual-tone mask to form a photoresist pattern layer; FIG. 2C is a cross section view showing the substrate after etching the substrate of FIG. 2B; FIG. 2D is a cross section view showing the substrate after ashing the photoresist pattern layer on the substrate of FIG. 2C; FIG. 2E is a cross section view showing the substrate after etching the substrate of FIG. 2D; FIG. 2F is a cross section view showing the substrate after removing the photoresist pattern layer of FIG. 2E.
As shown in FIG. 1, the array substrate of liquid crystal display comprises a pixel region 101, a non-display region and a TFT region 102. The non-display region comprises a wiring region and other regions located between the pixel regions 101. The TFT region 102 comprises a TFT channel region 1021, a source electrode region 1022 and a drain electrode region 1023. The wiring region comprises a gate line region 103 and a data line region 104. The pixel region 101 is the region formed by a plurality of pixel electrodes 141, the gate line region 103 is the region formed by a plurality of gate lines 11, and the data line region 104 is the region formed by a plurality of data lines 16.
Hereinafter, the conventional for manufacturing an array substrate of liquid crystal display will be described with reference to FIG. 2A-2F. Specifically, the method comprises the steps as follows.
Step 1 of depositing a first transparent conductive layer 14 and a metal layer 15 for source/drain electrodes in this order on a substrate 10 formed with a gate line 11 with integrated gate electrode 111, an insulating layer 12 and an active layer pattern 13, as shown in FIG. 2A;
Step 2 of depositing a photoresist layer and forming a photoresist pattern layer 100 through a dual-tone mask by exposing and developing process, wherein the thickness of the photoresist pattern layer 100 in the pixel region 101 is smaller than the thickness of the photoresist pattern layer 100 in the source electrode region 1022, the drain electrode region 1023 and the data line region 104, as shown in FIG. 2B;
Step 3 of performing a wet-etching process on a large area of the substrate 10 so that the metal layer 15 for source/drain electrodes, the first transparent conductive layer 14 and a portion of the active layer in the exposed region of the substrate 10 are etched to form a source electrode 151 and a TFT channel 131 respectively, as shown in FIG. 2C;
Step 4 of performing an ashing process on the photoresist pattern layer 100 to expose the metal layer 15 in the pixel region 101, as shown in FIG. 2D;
Step 5 of performing a wet-etching process on a large area of the substrate 10 so that the metal layer 15 for source/drain electrodes in the exposed region of the substrate 10 is etched to form a pixel electrode 141 and a drain electrode 152, as shown in FIG. 2E; and
Step 6 of removing the remaining photoresist pattern layer, as shown in FIG. 2F.
In the above-described step 3 and step 5, two etching processes on a large area of the substrate are required for forming the TFT channel, the source electrode, the drain electrode and the pixel electrode. Furthermore, in the case of performing etching on a large area, only the wet-etching process is feasible, that is, the substrate is immersed into the etching solution and the portion which is not covered by the photoresist is etched by the etching solution. Since the TFT channel region is wet-etched twice in the above method and it is difficult to control the degree of etching in the wet-etching process, the problem of over-etching the TFT channel occurs.